The present invention relates to electrostatic discharge (ESD) protection structures and more particularly to ESD protection transistor structures for deep-quarter micron line geometries.
Electrostatic discharges (ESDs) are high-voltage spikes of static charges which damage modem integrated circuits. ESDs are a significant failure mechanism, particularly as integrated circuit physical dimensions continue to shrink to the deep-quarter micron range.
Electrically, an ESD occurs upon contact of one or more of the terminals of an integrated circuit with a body or material that is statically charged to a high voltage. This level of static charge is readily generated by the triboelectric effect, and other mechanisms acting upon humans, equipment, or the circuits themselves. Upon contact, the integrated circuit discharges through its active devices and DC current paths. If the amount of charge is excessive however, the discharge current density can permanently damage the integrated circuit so that it is no longer functional or so that it is more prone to later-life failure. ESD damage thus is a cause of yield loss in manufacturing and also poor reliability in use.
In the past, n-type metal oxide semiconductor (NMOS) transistors have been widely used as the primary component in ESD protection circuits in semiconductor integrated circuit devices. Under ESD stress conditions, the NMOS transistor behavior changes drastically from normal operation. The actual conduction mechanism is that of bipolar action in a parasitic lateral bipolar structure.
In advanced manufacturing processes with transistors having lightly doped drain (diffusion) junctions, the NMOS performance is limited because the peak heating occurs close to the surface of the transistor in the silicon which has poor thermal conductivity. Therefore, an ESD implant has to be used to make the junction deeper as well as to overdope the lightly doped region of the diffusion for improved ESD performance. Further, the thin oxide is easily damaged, especially for the ESD paths near the interface of the thin oxide and the p-substrate.
It is also well known that salicidation (self-aligned siliciding) of the drain and source junctions reduces ESD performance significantly due to discharge current localization. From the ESD viewpoint, the primary effect of the salicidation is to bring a transistor drain or a source contact closer to its diffusion edge near their respective gate edge. The consequence is that under high current conditions, the ballasting resistance between the drain or the source contact and their respective gate edge is reduced and the short current path causes xe2x80x9chot spotxe2x80x9d formation, usually at the gate edge. Once a hot spot is formed, there is very little resistance to prevent current localization through the hot spot and so most of the current flows through the silicide to the gate edge. This leads to higher power dissipation and damage in this region. Also, the high power dissipation through the drain or source silicide can cause damage at the drain or source contact when the eutectic temperature of the silicide is exceeded.
The most conventional solution to the salicidation problem is called a xe2x80x9csalicide blockxe2x80x9d. Most salicidation fabrication technology processes have a xe2x80x9csalicide blockxe2x80x9d option, which is an additional photolithographic process step to block the formation of silicide in areas close to a transistor""s gate edge. Without the gate edge silicide, an ESD implantation is required make the drain junction deeper as well as to overdope the lightly doped region of the diffusion for better ESD performance. Since the ESD implantation is undesirable in the integrated circuits being protected, an ESD implant block would be required over the non-ESD circuits. Thus, this approach adds to process complexity because it requires at least two additional photolithographic process steps; i.e., the silicide block and the ESD implant block.
In the parasitic lateral bipolar structure of the NMOS transistor, the majority of the electrons reaching the collector junction are emitted from the emitter junction sidewall of the diffusion region, which results in a very small xe2x80x9cintrinsicxe2x80x9d base area. The high current is confined to a very small region of the emitter and base regions which leads to a large power density in these regions and hence higher temperatures.
The substrate current initially needs to forward-bias a small region of the source-substrate junction to turn xe2x80x9conxe2x80x9d the bipolar action. However, for better ESD performance, a larger emitter area is preferred. This will be particularly effective if the source barrier lowering occurs deeper in the junction, allowing the power dissipation to take place deeper in the device to reduce the temperature rise in the device.
In an ESD transistor, the voltage necessary to turn the transistor xe2x80x9conxe2x80x9d is reached before the occurrence of a gate oxide breakdown due to voltage across an internal integrated circuit gate oxide. Unfortunately, as these transistors continue to shrink in size down to the deep-quarter-micron geometry level, the gate oxide becomes so thin that the gate oxide breakdown voltage approaches the turn-on voltage. Thus, the protection window tends to go to zero and at a small enough geometry will provide no protection at all.
Looking back, the field oxide device (FOD) is a better protection element for large feature size technologies since the bipolar action takes place deeper in the silicon and the peak heating is located further away from the silicon surface. However, in advance processes with shallow junctions, the FOD performance is limited and the onset of damage has been observed at low-voltage levels.
Thus, if the turn-on voltage of the FOD could be lower and the snap-back breakdown of the FOD could be controlled to be further away from the silicon surface, the FOD might be again useable to provide ESD protection with a smaller layout area. This ideal has been long sought, but has also equally as long eluded those skilled in the art.
The present invention provides an electrostatic discharge protection structure with a dielectric gate, source and drain contacts, and a semiconductor substrate. The semiconductor substrate is of a first conductivity type having the dielectric gate disposed partially on its surface. The source and drain contacts are connected to source and drain diffusion regions of a second conductivity type separated by the dielectric gate. Deep source and drain wells of the second conductivity type respectively disposed under the source and drain diffusion regions define a channel region of the first conductivity type. The channel region is doped so that the surface breakdown voltage is exceeded before the subsurface depletion region punch-through voltage between the deep source and drain wells upon an electrostatic discharge at the drain contact. The structure is less subject to heat damage and provides excellent ESD protection in a small layout area.
The present invention further provides an electrostatic discharge protection structure with a dielectric gate, source and drain contacts, and a semiconductor substrate connected to a bonding pad on a dielectric layer containing a polysilicon tab and disposed over a floating well in the semiconductor substrate. The semiconductor substrate is of a first conductivity type having the dielectric gate disposed partially on its surface. The source and drain contacts are connected to source and drain diffusion regions of a second conductivity type separated by the dielectric gate. Deep source and drain wells of the second conductivity type respectively disposed under the source and drain diffusion regions define a channel region of the first conductivity type. The channel region is doped so that the surface breakdown voltage is exceeded before the subsurface depletion region punch-through voltage between the deep source and drain wells upon an electrostatic discharge at the drain contact. The structure includes a bonding pad connected to the drain contact and disposed over a dielectric layer containing a polysilicon tab. The dielectric layer in turn is disposed over a floating well in the semiconductor substrate. After wafer probing and wire bonding, the surface of the bonding pad is often punched with holes through the metal layer and have microcracks in the dielectric layer. These holes and microcracks help generate high electrical fields in the damaged dielectric layer and cause metal spiking when a high-voltage ESD is applied to the bonding pad. The polysilicon tab and the floating well provide protection against the ESD induced metal spiking.